[AISWorld] CFP- DPNoC 2016 (Scopus) & IJCDS SI (IET's INSPEC)

[Wael Elmedany]

Dear Colleague,

We are pleased to invite you to participate in the DPNoC 2016, *Montreal,
Quebec, Canada**, please see the CFP below:*


*------------------------------*---- CFP DPNoC 2016
*------------------------------**------*
The 3rd International Workshop on Design and Performance of Networks on
Chip
(DPNoC 2016)
http://www.intnoc.org/dpnoc16/


*August 15-18, 2016, Montreal, Quebec, Canada*

in conjunction with the

The 11th International Conference on Future Networks and Communications
(FNC 2016) <http://cs-conferences.acadiau.ca/fnc-16/>

http://cs-conferences.acadiau.ca/fnc-16/



*SCOPE AND OBJECTIVES*

The advance in silicon technology has led to the emergence of on-Chip
Systems (SoC), where a complete system with a large number of intellectual
property cores can be integrated onto a single silicon chip. The
performance of SoCs highly depends on the speed and efficiency of their
underlying communications subsystems. The light weight networks, known as
Network-on-Chip (NoC), have been introduced to overcome the scalability
problem found in shared-bus communication architectures. Intensive research
studies have been undertaken investigating the design cost, in terms of
silicon area and power consumption, and performance of NoC. Most of these
studies are targeting NoC topology, router microarchitecture, switching
techniques, routing algorithms, and application mapping onto NoC.



The workshop on the Design and Performance of Networks on Chip (DPNoC'2016)
will represent an international forum for researchers from both academia
and industry to expose the latest trends, research findings, and emerging
issues in this area.

*The Workshop topics include (but are not limited to) the following:*



   - Technology constraints on NoCs
   - Router microarchitecture
   - Flow control techniques
   - Switching techniques
   - Routing protocols
   - Fault tolerance/reliability in NoC
   - Technology constraints on NoCs
   - Scheduling and application mapping onto NoC
   - Wireless NoCs
   - NOCs modeling and performance evaluation
   - NOC  scalability
   - FPGA-based implementation of reconfigurable NoCs

*Journal Special Issue*

Extended version of all accepted papers in the workshop will be published
as special issue on The International Journal of Computing and Digital
Systems (IJCDS) <http://journals.uob.edu.bh/computing>

*Journal Special Issue*
<http://journals.uob.edu.bh/computing>

Extended version of all accepted papers in the workshop will be published
as special issue on <http://journals.uob.edu.bh/computing>The International
Journal of Computing and Digital Systems (IJCDS)
<http://journals.uob.edu.bh/ijcds>
<http://journals.uob.edu.bh/computing>
<http://journals.uob.edu.bh/computing>





        *INSTRUCTIONS FOR PAPER SUBMISSIONS*:

You are invited to submit original and unpublished research works on above
and other topics related to Design and Performance of Networks on Chip.
Submitted papers must not have been published or simultaneously submitted
elsewhere. Please, indicate clearly the corresponding author and include up
to 6 keywords and an abstract of no more than 400 words.


*Publication: * All DPNoC-2016 accepted papers will be printed in the
conference proceedings published by Elsevier Science in the open-access
Procedia Computer Science series on-line. Procedia Computer Sciences is
hosted on www.Elsevier.com
<http://www.journals.elsevier.com/procedia-computer-science> and on
Elsevier content platform ScienceDirect (www.sciencedirect.com
<http://www.sciencedirect.com/science/journal/18770509>), and will be
freely available worldwide. All papers in Procedia will also be indexed by
Thomson Reuters' Conference Proceeding Citation Index
http://thomsonreuters.com/conference-proceedings-citation-index/. The
papers will contain linked references, XML versions and citable DOI
numbers. You will be able to provide a hyperlink to all delegates and
direct your conference website visitors to your proceedings. All accepted
papers will also be indexed in DBLP (http://dblp.uni-trier.de/
<http://dblp.uni-trier.de/db/journals/procedia/procedia5.html#ShakshukiY11>
).



*IMPORTANT DATES*

Submission Deadline:

March 30, 2016

Authors Notification:

May 1, 2016

Final Manuscript Due:

June 14, 2016



*WORKSHOP Chairs*

*Dr. Wael M El-Medany*
Department Of Computer Engineering,
University Of Bahrain,  Bahrain
welmedany at uob.edu.bh

*      Dr. Samia Loucif*
      Software Engineering Department
      ALHOSN  University , UAE
      samia.loucif at ieee.org



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