[AISWorld] CFP- RSoC 2016 (IEEE Xplore) & IJCDS SI (IET's INSPEC)

[Wael Elmedany]

Dear Colleague,

We are pleased to invite you to participate in the RSoC 2016 , Lyon,
France, September 21-23, 2016*, please see the CFP below:*


*------------------------------**---- CFP *RSoC 2016
*------------------------------**------*


RSoC 2016 : SPECIAL SESSION ON Reconfigurable System on Chip
Link: http://mcsoc-forum.org/2016/wp-content/uploads/2016/02/CFP_RSoC-16.pdf

When Sep 21, 2016 - Sep 23, 2016
Where Lyon, France
Submission Deadline Mar 11, 2016
Notification Due Jun 24, 2016
Final Version Due Jul 15, 2016
*Categories* <http://www.wikicfp.com/cfp/allcat>    reconfigurable system
on chip
<http://www.wikicfp.com/cfp/call?conference=reconfigurable%20system%20on%20chip>
multi-processor architectures
<http://www.wikicfp.com/cfp/call?conference=multi-processor%20architectures>
embedded multicore
<http://www.wikicfp.com/cfp/call?conference=embedded%20multicore>   fpgas-based
system <http://www.wikicfp.com/cfp/call?conference=fpgas-based%20system>


Call For Papers

Advances in chip design technology permit increasingly complex applications
to be realized using reconfigurable systems-on-chips (RSOCs).
Multi-processor architectures are a promising solution to provide the
required computational performance for applications in the area of high
performance computing. Reconfigurable multiprocessor systems are a
particular type of embedded system, implemented using reconfigurable
hardware. RSoCs workshop address advanced topics in system design and
reconfigurable architecture. The workshop is organized in conjunction with
the IEEE 10th International Symposium on Embedded Multicore/Many-core
Systems-on-Chip (MCSoC-16), Lyon Congress Center, Lyon, France.. Authors
are invited to submit high quality papers representing original work from
both the academia and industry in (but not limited to) the following topics
focusing on reconfigurable systems-on-chips:

 Reconfigurable System-on-Chip Design
 High Performance Reconfigurable System-on-Chip
 Reconfigurable Embedded Systems
 FPGAs-based Reconfigurable Systems-on-Chip
 Applications for Reconfigurable Systems-on-Chip in Telecommunication
Networks
 Modeling Reconfigurable Systems-on-Chips
 Reconfigurable Multiprocessor Systems
 Reconfigurable network-on-chip Architecture
 Partial and Dynamic Reconfigurable FPGAs
 System Level Design of Reconfigurable Systems-on-Chip
 Hardware Security for Reconfigurable Systems-on-Chip
 Advanced Reconfigurable Computing

Submission guidelines:
Submissions must be in PDF and should not exceed 8 pages. The submission
must adhere to the two- column IEEE style using 10 pt. fonts. The page
limit includes all figures and references. All pages should be numbered.
Please make use of the following link to help you in the preparation and
submission of your final manuscript:
http://www.computer.org/portal/web/cscps/submission

Online submission page: https://edas.info/newPaper.php?c=21730&track=79336

Publication:
Proceedings will be published by the IEEE CPS in the same volume of the
main track. Authors of accepted papers are expected to register and present
their papers at the symposium. Symposium proceedings will be included in
the Computer Society Digital Library CSDL and IEEE Xplore. All CPS
conference publications are also submitted for indexing to EI’s Engineering
Information Index, Compendex, and ISI Thomson’s Scientific and Technical
Proceedings, ISTP/ISI Proceedings, and ISI Thomson.

Journal Special Issue:
Authors of selected papers will be invited to submit extended article
versions to The International Journal of Computing and Digital Systems
(IJCDS)
Contacts:


Session Chair:
Dr. Wael M El-Medany, University Of Bahrain, Bahrain
welmedany at uob.edu.bh