[AISWorld] CFP: DPNoC-2018 -The 5th International Workshop on Design and Performance of Networks on Chip

[DPNoC 2018]

 *********Apologies for multiple postings of this announcement*************



*CALL FOR PAPERS*
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---------------------------------

The 5th International Workshop on Design and Performance of Networks on
Chip (DPNoC-2018)

http://research-uob.org/dpnoc18/



To be held in conjunction with  the 13th International Conference on Future
Networks and Communications, Gran Canaria, Spain, August 13-15, 2018,

http://cs-conferences.acadiau.ca/fnc-18/





*Important Dates:*

Paper Submission Due:







March 20, 2018



Author Notification

 May 10, 2018

Finial Manuscript Due:

 May 28, 2018







*Scope*

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The advance in silicon technology has led to the emergence of on-Chip
Systems (SoC), where a complete system with a large number of intellectual
property cores can be integrated onto a single silicon chip. The
performance of SoCs highly depends on the speed and efficiency of their
underlying communications subsystems. The light weight networks, known as
Network-on-Chip (NoC), have been introduced to overcome the scalability
problem found in shared-bus communication architectures. Intensive research
studies have been undertaken investigating the design cost, in terms of
silicon area and power consumption, and performance of NoC. Most of these
studies are targeting NoC topology, router microarchitecture, switching
techniques, routing algorithms, and application mapping onto NoC.



The workshop on the Design and Performance of Networks on Chip (DPNoC'2018
will represent an international forum for researchers from both academia
and industry to expose the latest trends, research findings, and emerging
issues in this area.



The topics of interest include, but are not limited to:



   - Technology constraints on NoCs
   - Router microarchitecture
   - Flow control techniques
   - Switching techniques
   - Routing protocols
   - Fault tolerance/reliability in NoC
   - Technology constraints on NoCs
   - Scheduling and application mapping onto NoC
   - Wireless NoCs
   - NOCs modeling and performance evaluation
   - NOC  scalability
   - FPGA-based implementation of reconfigurable NoCs





*Paper Preparation, Submission and Publication*

*----------------------------------------------------------*

You are invited to submit original and unpublished research works on above
and other topics related to Design and Performance of Networks on Chip.
Submitted papers must not have been published or simultaneously submitted
elsewhere. Please, indicate clearly the corresponding author and include up
to 6 keywords and an abstract of no more than 400 words.

The submitted paper must be formatted according to the guidelines of
Procedia Computer Science
<http://www.elsevier.com/journals/procedia-computer-science/1877-0509/guide-for-authors>
, *MS Word Template*, Latex
<http://cs-conferences.acadiau.ca/fnc-15/templates/ecrc-procs.rar>, Template
Generic
<http://cs-conferences.acadiau.ca/fnc-15/templates/FNC-Template-Generic.pdf>,
Elsevier.

Paper Length must be no longer than 6 pages including all figures, tables
and references.

Paper Submission: authors are requested to submit their papers
electronically using the The Online EDAS conference management system
(https://edas.info/newPaper.php?c=23170)
<https://edas.info/newPaper.php?c=23170> in PDF format before the deadline
(see Important Dates). The submission processes will be managed by EDAS
<https://edas.info/>. If you have used this system before, you can use the
same username and password. If this is your first time using EDAS, you will
need to register for an account by clicking "create a new account"
<https://edas.info/newPerson.php?noauth=1> button. Upon completion of
registration, you will get a notification email from the system and you are
ready for submitting your paper. You can upload and re-upload the paper to
the system by the submission due date.

All accepted papers will be scheduled for oral presentations and will be
printed in the conference proceedings published by Elsevier Science in the
open-access Procedia Computer Science series (on-line). At least one author
of each accepted paper is required to register and attend the conference to
present the work.



All DPNoC-2018 accepted papers will be printed in the conference
proceedings published by Elsevier Science in the open-access Procedia
Computer Science series on-line. Procedia Computer Sciences is hosted on
www.Elsevier.com
<http://www.journals.elsevier.com/procedia-computer-science> and on
Elsevier content platform ScienceDirect (www.sciencedirect.com
<http://www.sciencedirect.com/science/journal/18770509>), and will be
freely available worldwide. All papers in Procedia will also be indexed by
Thomson Reuters' Conference Proceeding Citation Index http://thomsonreuters.
com/conference-proceedings-citation-index/. The papers will contain linked
references, XML versions and citable DOI numbers. You will be able to
provide a hyperlink to all delegates and direct your conference website
visitors to your proceedings. All accepted papers will also be indexed in
DBLP (http://dblp.uni-trier.de/
<http://dblp.uni-trier.de/db/journals/procedia/procedia5.html#ShakshukiY11>
).

Journal Special Issue: extended version of all accepted papers in the
workshop will be published as special issue on The International Journal of
Computing and Digital Systems (IJCDS) <http://journals.uob.edu.bh/ijcds> Papers
must be formatted according to IJCDS form
<http://journals.uob.edu.bh/IJCDS/for-authors>.



*DPNoC-2018 Workshop Co-Chairs*