[AISWorld] Newly published papers of JCSE (Jun. 2018)

[office at kiise.org]

Dear Colleague:

 

We are pleased to announce the release of a new issue of Journal of
Computing Science and Engineering (JCSE), published by the Korean Institute
of Information Scientists and Engineers (KIISE). KIISE is the largest
organization for computer scientists in Korea with over 4,000 active
members. 

 

Journal of Computing Science and Engineering (JCSE) is a peer-reviewed
quarterly journal that publishes high-quality papers on all aspects of
computing science and engineering. JCSE aims to foster communication between
academia and industry within the rapidly evolving field of Computing Science
and Engineering. The journal is intended to promote problem-oriented
research that fuses academic and industrial expertise. The journal focuses
on emerging computer and information technologies including, but not limited
to, embedded computing, ubiquitous computing, convergence computing, green
computing, smart and intelligent computing, and human computing. JCSE
publishes original research contributions, surveys, and experimental studies
with scientific advances.

 

Please take a look at our new issue posted at http://jcse.kiise.org
<http://jcse.kiise.org/> . All the papers can be downloaded from the Web
page.

 

The contents of the latest issue of Journal of Computing Science and
Engineering (JCSE)

Official Publication of the Korean Institute of Information Scientists and
Engineers

Volume 12, Number 2, June 2018

 

pISSN: 1976-4677

eISSN: 2093-8020

 

* JCSE web page: http://jcse.kiise.org

* e-submission: http://mc.manuscriptcentral.com/jcse

 

Editor in Chief: Insup Lee (University of Pennsylvania)

Il-Yeol Song (Drexel University) 

Jong C. Park (KAIST)

Taewhan Kim (Seoul National University)

 

 

JCSE, vol. 12, no. 2, June 2018

 

[Paper One]

- Title: Packing Narrow-Width Operands to Improve GPU Performance

- Authors: Xin Wang and Wei Zhang

- Keyword: GPU register file; Narrow-width operand; Dynamic register packing

 

- Abstract

Graphics processing units (GPUs), originally designed for graphics
applications, have become a popular platform to accelerate general purpose
computations. By exploiting massive thread-level parallelism (TLP), GPUs can
achieve high throughput as well as memory latency hiding. A GPU typically
employs a very large register file (RF) in order to support fast and
low-cost context switching between tens of thousands of active threads. As a
result, exploiting the RF efficiently is critical for the GPU to achieve
high performance. We observe that for many GPGPU applications, a large
percentage of computed results actually have fewer significant bits compared
to the full width of a 32-bit register, and thus propose a GPU register
packing scheme to dynamically exploit narrow-width operands and pack
multiple operands into a single full-width register. By using dynamical
register packing, more RF space becomes available which allows the GPU to
enable more TLP through assigning additional thread blocks on streaming
multiprocessors (SMs), and thus improve performance. Our experimental
results indicate that dynamic register packing can improve GPU performance
by up to 1.96X, and by 1.18X on average.

 

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 2, pp.37-49
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=306&page_url=Cur
rent_Issues> 

 

[Paper Two]

- Title: Improving CPU and GPU Performance through Sample-Based Dynamic LLC
Bypassing

- Authors: Xin Wang and Wei Zhang

- Keyword: Cache bypassing; Last level cache; Heterogeneous CPU-GPU
architecture

 

- Abstract

The current trend toward integrated central processing units (CPUs) and
graphics processing units (GPUs) on the same chip presents new challenges
for the efficient and fair sharing of resources. Unlike traditional
multicores, CPU and GPU cores in the integrated architecture can generate
diverse cache traffics and exhibit quite different temporal or spatial data
localities. The shared last-level cache (LLC) between the two can result in
a large amount of interference between CPU and GPU LLC accesses, thus
impacting the performance of both the CPUs and GPUs. Cache bypassing is a
promising method to improve LLC performance and to alleviate resource
contention between CPUs and GPUs. However, inefficient cache bypassing may
lead to significant Network on Chip (NoC) traffic congestion and subsequent
performance degradation, particularly for a CPU on a heterogeneous CPU-GPU
system with an on-chip ring network. To manage the LLC more efficiently, we
propose a sample-based dynamic cache bypassing method for shared LLC in
heterogeneous CPU-GPU multicore systems. This method samples the LLC miss
rates and NoC traffics for both the CPU and GPU at run-time and uses a
statistical bypassing decision-making model to intelligently decide whether
to bypass or not. Our experiments show that bypassing CPU can be more useful
than bypassing GPU for integrated CPU-GPU architecture with ring-based NoC
topology. Our results indicate that bypassing both CPU and GPU can improve
CPU performance by 34.30% and GPU performance by 3.20%, while bypassing CPU
alone enhances CPU performance by 38.09% and GPU performance by 1.11%, and
bypassing GPU alone increases CPU performance by 4.12% and GPU performance
by 2.60%, on average.

 

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 2, pp.50-62
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=307&page_url=Cur
rent_Issues> 

 

[Paper Three]

- Title: Interval Disaggregation with Product Life Cycles and Constraints

- Authors: Sunho Lee, Cheol Ryu, Sang Kyun Cha, Kunsoo Park, Jungsuk Oh,
Kihong Kim, and Changbin Song

- Keyword: Disaggregation; Product life cycles; Constraints; Nonlinear
regression

 

- Abstract

Disaggregation is a common operation in business applications. One of the
main disaggregation operations in use has been referential disaggregation,
but a more advanced disaggregation operation called interval disaggregation
has recently been introduced. In this paper we significantly generalize the
model of interval disaggregation in the previous work. Through nonlinear
regression, we apply interval disaggregation to the products with product
life cycle curves. We implemented interval disaggregation with product life
cycles as a relational operator in a commercial in-memory database system
and did experiments on real-world data. Our experiments show that interval
disaggregation with product life cycles outperforms previous disaggregation
operations. We also present a technique that combines constraints such as
factory capacities into interval disaggregation, so that we can find a
product mix that maximizes profit subject to the constraints.

 

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 2, pp.63-76
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=308&page_url=Cur
rent_Issues> 

 

[Paper Four]

- Title: Design and Analysis of Improved Iris-Based Gaze Estimation Model

- Authors: Anjana Sharma and Pawanesh Abrol

- Keyword: Iris center based gaze estimation (ICGE) model; Adaptive
thresholding; Iris center; Non-intrusive; Gaze quadrant detection; Glint

 

- Abstract

The detection accuracy of gaze direction mainly depends on the performance
of features extracted from eye images. Limitations on the estimation of gaze
direction include harmful infrared (IR) light, expensive devices, static
thresholding, inappropriate and complex segmentation techniques, corneal
reflections, etc. In this study, an efficient appearance cum feature-based
detection model, namely, iris center-based gaze estimation (ICGE), has been
proposed. The model is an extension of the earlier proposed glint-based gaze
direction estimation (GDE) model and overcomes the above limitations. The
ICGE model has been analyzed for GDE based on iris center coordinates using
a local adaptive thresholding technique. An indigenous database using more
than two hundred images of different subjects on a five quadrant map screen
generates almost 90% accurate results for iris and gaze quadrant detection.
The distinguishing features of the low cost, non-intrusive proposed model
include a lack of IR and affordable ubiquitous H/W designing, large
subject-camera distance and screen dimensions, no glint dependency, and many
more. The proposed model also shows significantly better results in the
lower periphery corners of the quadrant map than traditional models. In
addition, aside from the comparison with the GDE model, the proposed model
has also been compared with other existing techniques.

 

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 2, pp.77-89
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=309&page_url=Cur
rent_Issues> 

 

 

[Call For Papers]

Journal of Computing Science and Engineering (JCSE), published by the Korean
Institute of Information Scientists and Engineers (KIISE) is devoted to the
timely dissemination of novel results and discussions on all aspects of
computing science and engineering, divided into Foundations, Software &
Applications, and Systems & Architecture. Papers are solicited in all areas
of computing science and engineering. See JCSE home page at
http://jcse.kiise.org <http://jcse.kiise.org/>  for the subareas.

The journal publishes regularly submitted papers, invited papers, selected
best papers from reputable conferences and workshops, and thematic issues
that address hot research topics. Potential authors are invited to submit
their manuscripts electronically, prepared in PDF files, through
<http://mc.manuscriptcentral.com/jcse> http://mc.manuscriptcentral.com/jcse,
where ScholarOne is used for on-line submission and review. Authors are
especially encouraged to submit papers of around 10 but not more than 30
double-spaced pages in twelve point type. The corresponding author's full
postal and e-mail addresses, telephone and FAX numbers as well as current
affiliation information must be given on the manuscript. Further inquiries
are welcome at JCSE Editorial Office,  <mailto:office at kiise.org>
office at kiise.org (phone: +82-2-588-9240; FAX: +82-2-521-1352).