[AISWorld] Newly published papers of JCSE (Dec. 2018)

Fri Dec 28 08:38:10 EST 2018

Dear Colleague:

We are pleased to announce the release of a new issue of Journal of
Computing Science and Engineering (JCSE), published by the Korean Institute
of Information Scientists and Engineers (KIISE). KIISE is the largest
organization for computer scientists in Korea with over 4,000 active
members. 

Journal of Computing Science and Engineering (JCSE) is a peer-reviewed
quarterly journal that publishes high-quality papers on all aspects of
computing science and engineering. JCSE aims to foster communication between
academia and industry within the rapidly evolving field of Computing Science
and Engineering. The journal is intended to promote problem-oriented
research that fuses academic and industrial expertise. The journal focuses
on emerging computer and information technologies including, but not limited
to, embedded computing, ubiquitous computing, convergence computing, green
computing, smart and intelligent computing, and human computing. JCSE
publishes original research contributions, surveys, and experimental studies
with scientific advances.

Please take a look at our new issue posted at http://jcse.kiise.org
<http://jcse.kiise.org/> . All the papers can be downloaded from the Web
page.

The contents of the latest issue of Journal of Computing Science and
Engineering (JCSE)

Official Publication of the Korean Institute of Information Scientists and
Engineers

Volume 12, Number 4, December 2018

pISSN: 1976-4677

eISSN: 2093-8020

* JCSE web page: http://jcse.kiise.org 

* e-submission: http://mc.manuscriptcentral.com/jcse 

Editor in Chief: Insup Lee (University of Pennsylvania)

Il-Yeol Song (Drexel University) 

Jong C. Park (KAIST)

Taewhan Kim (Seoul National University)

JCSE, vol. 12, no. 4, December 2018

[Paper One]

- Title: Estimating the Worst-Case Execution Time of the Shared Data Cache
in Integrated CPU-GPU Architectures

- Authors: Yijie Huangfu and Wei Zhang

- Keyword: Graphics Processing Units (GPUs); Worst-Case Execution Time
(WCET); Cache memories; Integrated CPU-GPU

- Abstract

Integrated CPU-GPU architectures have the potential to increase performance
and energy efficiency for a variety of applications, due to their tight
coupling of the CPU and GPU cores. However, in order to serve hard real-time
and safety critical applications, the integrated CPU-GPU architecture must
be time-predictable and worst-case execution time (WCET) analyzable. In this
work, we study the shared data last-level cache (LLC) in the integrated
CPU-GPU architecture and propose an access interval-based method in order to
estimate the worst-case cache misses of the LLC. The results indicate that
the proposed technique can effectively improve the accuracy of the miss rate
estimation in the LLC. We also find that the improved LLC miss rate
estimations can be used to further improve the WCET estimations of the GPU
kernels running on the integrated CPU-GPU architecture.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 4, pp.139-148
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=318&page_url=Cur
rent_Issues> 

[Paper Two]

- Title: CNN-Based Drug Recognition and Braille Embosser System for the
Blind

- Authors: Soyeong Lee, Sunhae Jung, and Hyunjoo Song

- Keyword: Human-computer interaction; Deep learning; Drug recognition;
Braille embosser

- Abstract

Visual impairments reduce one's ability to perform daily tasks such as
taking medicine. While the sighted can use their vision to effortlessly
locate and identify drugs, the blind must rely on external assistance to
complement their visual sense. Thus, receiving appropriate aid at the right
time is crucial to avoid the misuse of drugs. We conducted interviews
regarding medicine intake with 30 partially or completely blinded persons
registered at three supporting facilities. Participants reported limitations
of their current methods in finding their medication which led to them
taking unintentional irregular doses caused by the lack of aid. Based on the
results of the interview, we developed a drug recognition model and braille
embosser system for Android smartphones. Using a picture of a medicine taken
with a built-in camera, the CNN-based recognition model can classify 11
types of medicines with 99.6% accuracy. In addition, a low-cost braille
embosser, which can connect to one's smartphone via Bluetooth, can print the
classification results as a braille label for future identification without
a smartphone.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 4, pp.149-156
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=319&page_url=Cur
rent_Issues> 

[Paper Three]

- Title: User-Centric Thermal Management for Smartphones

- Authors: Wook Song and Jihong Kim

- Keyword: Smartphone; Operating system; User-centric optimization; Thermal
management; Dynamic voltage and frequency scaling

- Abstract

For high-performance smartphones, keeping the on-chip temperature under a
given critical temperature is a major concern. In order to prevent the
temperature from rising above the critical point, modern smartphones widely
adopt the dynamic thermal management (DTM) scheme, which limits the maximum
CPU frequency when the CPU reaches high temperatures (thus making the CPU
temperature drop). In this paper, we propose a novel DTM scheme based on
user-perceived response time analysis called SmartDTM. Unlike existing DTM
schemes that can significantly degrade the quality of user experience,
SmartDTM explicitly accounts for the quality of the user experience in
making DTM decisions. We divide an execution of a given user-interactive
session into two intervals, one where the system response time directly
affects the user experience and the other where the system response time
does not affect the user experience. In the user-perceived response time
interval, our proposed scheme conservatively makes DTM decisions so that the
quality of the user experience is not affected by the reduced maximum CPU
frequency. On the other hand, in the user-oblivious response time interval,
SmartDTM aggressively lowers the CPU frequency so that the CPU temperature
can be quickly decreased to a safe level without negatively affecting user
experience. Our experimental results on an ODROID-XU+E board show that
SmartDTM can improve the performances of user-perceived intervals by 12.2%
and 21.4% over the Android’s default DTM policy when the initial temperature
was set to 65°C and 70°C, respectively, under the critical temperature of
85°C.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 4, pp.157-169
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=320&page_url=Cur
rent_Issues> 

[Paper Four]

- Title: Exploring the Performance Impact of Emerging Many-Core
Architectures on MPI Communication

- Authors: Joong-Yeon Cho, Hyun-Wook Jin, and Dukyun Nam

- Keyword: Many-core; MPI; High-bandwidth memory; Processor interconnect;
Core affinity

- Abstract

As major architectural changes emerge to resolve the scalability issues in
many-core processors, it is critical to understand their impact on the
performance of parallel programming models and run-time supports. For
example, the Intel Xeon Phi KNL processor is equipped with a high-bandwidth
memory and deploys a mesh-based processor interconnect. In this paper, we
comprehensively analyze the impact of high-bandwidth memory and processor
interconnects on the message passing interface (MPI) communication
bandwidth. The results show that the bandwidth of MPI intra-node
communication can be improved up to 372% by exploiting the high-bandwidth
memory. In addition, we show that the bandwidth of MPI inter-node
communication can be improved up to 143% with optimal core affinity. Our
comprehensive study provides insight into optimization of the performance of
MPI communication in emerging many-core architectures.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 12, no. 4, pp.170-179
<http://jcse.kiise.org/PublishedPaper/year_abstract.asp?idx=321&page_url=Cur
rent_Issues> 

[Call For Papers]

Journal of Computing Science and Engineering (JCSE), published by the Korean
Institute of Information Scientists and Engineers (KIISE) is devoted to the
timely dissemination of novel results and discussions on all aspects of
computing science and engineering, divided into Foundations, Software &
Applications, and Systems & Architecture. Papers are solicited in all areas
of computing science and engineering. See JCSE home page at
http://jcse.kiise.org <http://jcse.kiise.org/>  for the subareas.

The journal publishes regularly submitted papers, invited papers, selected
best papers from reputable conferences and workshops, and thematic issues
that address hot research topics. Potential authors are invited to submit
their manuscripts electronically, prepared in PDF files, through
<http://mc.manuscriptcentral.com/jcse> http://mc.manuscriptcentral.com/jcse,
where ScholarOne is used for on-line submission and review. Authors are
especially encouraged to submit papers of around 10 but not more than 30
double-spaced pages in twelve point type. The corresponding author's full
postal and e-mail addresses, telephone and FAX numbers as well as current
affiliation information must be given on the manuscript. Further inquiries
are welcome at JCSE Editorial Office,  <mailto:office at kiise.org>
office at kiise.org (phone: +82-2-588-9240; FAX: +82-2-521-1352).