[AISWorld] IJERTCS: contents of latest issue, and Call for Papers

[Seppo Virtanen]

The contents of the latest issue of:

International Journal of Embedded and Real-Time Communication Systems 
(IJERTCS)
Official Publication of the Information Resources Management Association
Volume 4, Issue 2, April – June 2013
Published: Quarterly in Print and Electronically
ISSN: 1947-3176 EISSN: 1947-3184
Published by IGI Publishing, Hershey, Pennsylvania, USA
www.igi-global.com/ijertcs

Editor-in-Chief: Seppo Virtanen, University of Turku, Finland

EDITORIAL PREFACE

Seppo Virtanen, University of Turku, Finland

To obtain a copy of the Editorial Preface, click on the link below.

http://www.igi-global.com/pdf.aspx?tid%3D89257%26ptid%3D71487%26ctid%3D15%26t%3DEditorial%20Preface

 
PAPER ONE

Application Workload Modelling via Run-Time Performance Statistics

Subayal Khan (VTT Technical Research Centre of Finland, Oulu, Finland), 
Jukka Saastamoinen (VTT Technical Research Centre of Finland, Oulu, 
Finland), Jyrki Huusko (VTT Technical Research Centre of Finland, Oulu, 
Finland), Juha-Pekka Soininen (VTT Technical Research Centre of Finland, 
Oulu, Finland) and Jari Nurmi (Department of Computer Systems, Tampere 
University of Technology, Tampere, Finland)

Modern mobile nomadic devices for example internet tablets and high end 
mobile phones support diverse distributed and stand-alone applications 
that were supported by single devices a decade back. Furthermore the 
complex heterogeneous platforms supporting these applications contain 
multi-core processors, hardware accelerators and IP cores and all these 
components can possibly be integrated into a single integrated circuit 
(chip). The high complexity of both the platform and the applications 
makes the design space very complex due to the availability of several 
alternatives. Therefore the system designer must be able to quickly 
evaluate the performance of different application architectures and 
implementations on potential platforms. The most popular technique 
employed nowadays is termed as system-level-performance evaluation which 
uses abstract workload and platform capacity models. The platform 
capacity models and application workload models reside at a higher 
abstraction-level. The platform and application workload models can be 
instantiated with reduced modeling effort and also operate at a higher 
simulation speed. This article presents a novel run-time statistics 
based application workload model extraction and platform configuration 
technique. This technique is called platform COnfiguration and woRkload 
generatIoN via code instrumeNtation and performAnce counters (CORINNA) 
which offers several advantages over compiler based technique called 
ABSINTH, and also provides automatic configuration of the platform 
processor models for example cache-hits and misses obtained during the 
application execution.


To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/application-workload-modelling-via-run-time-performance-statistics/89259

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=89259


 
PAPER TWO

Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 
2D Mesh NoC using LBDRe

Renu Verma (Rama Institute of Technology, Kanpur, Uttar Pradesh, India), 
Mohammad Ayoub Khan (Centre for Development of Advanced 
Computing(C-DAC), Noida, Uttar Pradesh, India) and Amit Zinzuwadiya 
(Amdocs, Gurgaon, Haryana, India)

Efficient routing is challenging and crucial problem in the irregular 
mesh NoC topologies because of increasing hardware cost and routing 
tables. In this paper, the authors propose an efficient deadlock-free 
routing algorithm for irregular mesh NoCs which reduces the latency and 
power consumption significantly. The problem with degree priority based 
routing algorithm is that it cannot remove deadlocks in irregular mesh 
topologies. Therefore, the authors use the extended Logic Based 
Distributed Routing (LBDRe) to remove deadlock situations without using 
any virtual channel in the degree priority based routing algorithm. The 
proposed LBDRe based technique also removes the dependency on routing 
tables. The authors further apply odd-Even routing algorithm to LBDRe to 
ensure that some turns are prohibited to remove deadlocks. Experimental 
results show that the proposed routing algorithm reduces power 
consumption by 9–22% and overall average latency by 8–12% with the 
minimum hardware cost for the irregular mesh NoC topologies.


To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/power-and-latency-optimized-deadlock-free-routing-algorithm-on-irregular-2d-mesh-noc-using-lbdre/89260

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=89260


 
PAPER THREE

A Buffered Dual-Access-Mode Scheme Designed for Low-Power 
Highly-Associative Caches

Yul Chu (University of Texas Pan American, Edinburg, TX, USA) and Marven 
Calagos (University of Texas Pan American, Edinburg, TX, USA)

This paper proposes a buffered dual-access-mode cache to reduce power 
consumption for highly-associative caches in modern embedded systems. 
The proposed scheme consists of a MRU (most recently used) buffer table 
and a single cache structure to implement two accessing modes, phased 
mode and way-prediction mode. The proposed scheme shows better access 
time and lower power consumption than two popular low-power caches, 
phased cache and way-prediction cache. The authors used Cacti and 
SimpleScalar simulators to evaluate the proposed cache scheme by using 
SPEC benchmark programs. The experimental results show that the proposed 
cache scheme improves the EDP (energy delay product) up to 40% for 
instruction cache and up to 42% for data cache compared to 
way-prediction cache, which performs better than phased cache.


To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/a-buffered-dual-access-mode-scheme-designed-for-low-power-highly-associative-caches/89261

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=89261
 
PAPER FOUR

Time Petri Nets with Action Duration: A True Concurrency Real-Time Model

N. Belala (MISC Laboratory, Constantine II University, Constantine, 
Algeria), D.E. Saїdouni (MISC Laboratory, Constantine II University, 
Constantine, Algeria), R. Boukharrou (MISC Laboratory, Constantine II 
University, Constantine, Algeria), A.C. Chaouche (MISC Laboratory, 
Constantine II University, Constantine, Algeria), A. Seraoui (MISC 
Laboratory, Constantine II University, Constantine, Algeria) and A. 
Chachoua (MISC Laboratory, Constantine II University, Constantine, Algeria)

The design of real-time systems needs a high-level specification model 
supporting at the same time timing constraints and actions duration. The 
authors introduce in this paper an extension of Petri Nets called Time 
Petri Nets with Action Duration (DTPN) where time is associated with 
transitions. In DTPN, the firing of transitions is bound to a time 
interval and transitions represent actions which have explicit 
durations. The authors give an operational semantics for DTPN in terms 
of Durational Action Timed Automata (DATA). DTPN considers both timing 
constraints and durations under a true-concurrency semantics with an aim 
of better expressing concurrent and parallel behaviours of real-time 
systems.


To obtain a copy of the entire article, click on the link below.
http://www.igi-global.com/article/time-petri-nets-with-action-duration/89262

To read a PDF sample of this article, please visit
http://www.igi-global.com/viewtitlesample.aspx?id=89262

*****************************************************
For full copies of the above articles, check for this issue of the 
International Journal of Embedded and Real-Time Communication Systems 
(IJERTCS) in your institution's library.  This journal is also included 
in the IGI Global aggregated "InfoSci-Journals" database:
http://www.igi-global.com/EResources/InfoSciJournals.aspx.
*****************************************************

CALL FOR PAPERS

Mission of IJERTCS:

The mission of the International Journal of Embedded and Real-Time 
Communication Systems (IJERTCS) is to disseminate recent advancements 
and innovations in this interdisciplinary research area for field 
researchers, practitioners, scientists, academicians, students, and IT 
professionals. IJERTCS focuses on overcoming challenges involved in the 
rapid development of embedded communication systems towards feature-rich 
multimedia computers

Coverage of IJERTCS:

The International Journal of Embedded and Real-Time Communication 
Systems (IJERTCS) extensively covers research in the area of embedded 
and real-time communication systems. Within this field, topics to be 
discussed in the journal include (but are not limited to) the following:

Asynchronous and synchronous circuit techniques
Design methods
Embedded networks (built-in networks in embedded communication devices)
Emerging new topics
Fault-tolerant hardware and software technologies
Formal design and verification methods
Hardware and software solutions for protocol processing
Hardware and software solutions for real-time systems
Hardware platforms and technologies
Hardware/software co-design
Modeling and verification methods
On-chip communication in SoC and NoC
OWA (open wireless architecture)
Performance modeling
Platform based design
Real-time computing
Reconfigurable systems
Security issues and technologies
Single-chip SDR (software defined radio) solutions
Software design
Testing techniques

IGI Global is pleased to offer a special Multi-Year Subscription Loyalty 
Program. In this program, customers who subscribe to one or more 
journals for a minimum of two years will qualify for secure subscription 
pricing. IGI Global pledges to cap their annual price increase at 5%, 
which guarantees that the subscription rates for these customers will 
not increase by more than 5% annually.

Submission:

Prospective authors should note that only original and previously 
unpublished articles will be considered. INTERESTED AUTHORS MUST CONSULT 
THE JOURNAL’S GUIDELINES FOR MANUSCRIPT SUBMISSIONS at 
http://www.igi-global.com/journals/guidelines-for-submission.aspx PRIOR 
TO SUBMISSION. All article submissions will be forwarded to at least 3 
members of the Editorial Review Board of the journal for double-blind, 
peer review. Final decision regarding acceptance/revision/rejection will 
be based on the reviews received from the reviewers. All submissions 
must be forwarded electronically.

All inquiries regarding IJERTCS should be directed to the attention of:

Dr. Seppo Virtanen
Editor-in-Chief
International Journal of Embedded and Real-Time Communication Systems
Email: seppo.virtanen at utu.fi

All manuscript submissions to IJERTCS should be sent through the online 
submission system:
http://www.igi-global.com/authorseditors/titlesubmission/newproject.aspx